1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same. More specifically, the present invention relates to a semiconductor device that includes a three dimensional structure or a vertically extending structure such as a pillar structure. The pillar structure has upper and lower diffusion layers, and a conductor contacting the upper diffusion layer, wherein the conductor has a reduced contact resistance with the upper diffusion layer.
Priority is claimed on Japanese Patent Application No. 2008-110210, filed Apr. 21, 2008, the content of which is incorporated herein by reference.
2. Description of the Related Art
Dynamic random access memories (DRAMs) have an array of memory cells. Each memory cell includes a pair of a transistor and a capacitor. The degree of integration of memory cells in the DRAMs depends on the development of lithography technique. No further substantive increase in the degree of integration of memory cells can be available as long as the two dimensional array of memory cells is adopted and no further development of lithography technique is made. Namely, any further substantive increase in the degree of integration would be no longer available unless a three-dimensional structure or vertically extending structure is adopted.